• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    Each switching circuit (CCi) of the multiplexer comprises a first NMOS type switching module (5) having an on state and a blocked state and a second PMOS type switching module (6) having an on state and a off state, connected in parallel between the corresponding input (BEi) and the output (BS), a first control module (7) intended to be powered by a first supply voltage (Vdd) and configured to reduce the leakage currents of the first switching module (5) when the first switching module (5) is in its off state, a second control module (8) to be powered by a second supply voltage (Vmax) and configured to reduce the power supply currents. leakage of the second switching module (6) when the second switching module (6) is in its off state. At least one voltage selection circuit (CST) is configured to supply the second supply voltage (Vmax) equal to the largest of the first supply voltage (Vdd) and the voltages present at the input and output. exit.
    公开号:FR3030155A1
    申请号:FR1462317
    申请日:2014-12-12
    公开日:2016-06-17
    发明作者:Pawel Fiedorow；Thierry Masson
    申请人:STMicroelectronics Grenoble 2 SAS；
    IPC主号:
    专利说明:

    [0001] Analog Multiplexer Embodiments of the invention relate to analog multiplexers, and more specifically analog multiplexers capable of passing high voltage signals with low control voltages while being compatible with a so-called "cold spare" or "cold" mode. cold spare "according to an Anglo-Saxon name well known to those skilled in the art. Generally, an analog multiplexer comprises several channels respectively connecting several inputs to an output. Each channel typically includes a controllable CMOS circuit. When the multiplexer is powered, one of the channels is selected to transmit the signal present at the corresponding input to the output. When the multiplexer is in the "cold spare" mode, it is not powered, and it is likely to replace another multiplexer to which it is connected in the case where this other multiplexer is defective.
    [0002] However, in the "cold spare" mode, the multiplexer must not interfere with the operation of the other multiplexer, particularly in terms of power consumption. According to one embodiment, there is provided an analog multiplexer whose gate-source and substrate-source voltages of the analog switches are controlled so as to ensure the linearity and operation of the switches throughout the range of the input and output signals. and reduce as much as possible the leakage currents of the analog switches when they are in their off state.
    [0003] According to one embodiment, an analog multiplexer is also proposed whose high voltage analog switches are compatible with a low voltage control technology.
    [0004] According to another embodiment, it is still proposed an analog multiplexer compatible with the so-called "cold spare" mode. Thus, in one aspect, there is provided an analog multiplexer having a plurality of inputs and an output and a plurality of switching circuits respectively connected between the inputs and said output. According to a general characteristic of this aspect, each switching circuit comprises: a first NMOS type switching module 10 having an on state and a blocked state; a second PMOS type switching module having an on state and a blocked state; the first and second switching modules being connected in parallel between the corresponding input and the output; a first control module intended to be powered by a first supply voltage and configured to reduce the leakage currents of the first module of the first module; switching when the first switch module is in its off state, and 20 - a second control module for being powered by a second supply voltage and configured to reduce the leakage currents of the second switch module when the second switch module is switching is in its off state.
    [0005] In addition, the multiplexer comprises at least one voltage selection circuit configured to deliver said second supply voltage which is equal to the greater of the first supply voltage and the voltages present at the input and output. . This voltage selector circuit contributes to the smooth operation of the switching circuit in a normal operating mode (multiplexer powered) or in a "cold spare" mode. To be compatible with the so-called "cold spare" mode, the first control module and the second control module are also advantageously configured so that, when the first supply voltage is zero, the two modules of FIG. switching are blocked and any current consumption at the input and output is zero or almost zero (leaks close) and in practice below a threshold.
    [0006] This threshold depends essentially on the technology used and the geometry of the transistors and is advantageously determined by those skilled in the art so that the unpowered multiplexer (in "cold spare" mode) does not disturb the normal operation of the transistor. another multiplexer to which it is connected. This threshold may be for example of the order of 0.1% of a normal current consumption in the presence of the first non-zero supply voltage. As an indication this threshold may be of the order of 0.1 1.1A. The first switching module may advantageously comprise two extended drain NMOS transistors connected in series between the input and the output and having their sources and substrates mutually connected. Such an arrangement is commonly designated by the person skilled in the art under the acronym "back to back switch", which makes it possible to completely control the gate-source voltage of the two NMOS extended-drain transistors. In the same manner, the second switching module may comprise two extended drain PMOS transistors connected in series between the input and the output and having their sources and substrates mutually connected.
    [0007] Advantageously, the use of the two switch modules, respectively of the NMOS type and of the PMOS type, connected in parallel to the input and the output, makes it possible to cover the entire dynamic range of the input and output signals. Furthermore, since the input and the output are connected to the drains of the extended drain NMOS and PMOS transistors, higher input and output impedances can be obtained. According to one embodiment, the first control module comprises a first control block controllable by a first binary control signal and configured for when the first binary control signal has a first logic value, pull the gates to ground and the substrates of the NMOS transistors of the first switching module so as to place it in its off state. The first control module may further comprise a first input block connected to said corresponding input and configured for when the first binary control signal has its second logic corresponding to an on state of the first switching module, to control the voltages gate of the NMOS transistors of the first switching module to the voltage present at the input and limit these gate voltages to the first power supply voltage. According to another embodiment, said second control module is controllable by a second binary control signal, advantageously complementary to the first binary signal, and configured for when the second binary control signal has a first logic value, to fire at the second supply voltage, gates and substrates PMOS transistors of the second switching module so as to place it in its off state. The second control module can be further configured for when the second binary control signal has its second logic corresponding to an on state of the second switching module, leaving the sources and substrates of the PMOS transistors of the second floating switch module and applying on the gates of these PMOS transistors of the second switching module a gate voltage close to the first supply voltage. According to another embodiment, the voltage selection circuit of the analog multiplexer comprises an additional drained PMOS additional transistor whose gate is connected to its source by a resistor and supplied by a current source, the source of the additional transistor. being connected to said input and the output by diodes in reverse, the source being intended to deliver said second supply voltage. The analog multiplexer is advantageously integrated.
    [0008] Further advantages and features of the invention will be apparent from the detailed description of embodiments, given as non-limiting examples and illustrated by the accompanying drawings, in which: FIG. block diagram of an example of an analog multiplexer according to the invention, - Figures 2 to 3 relate to different embodiments of an analog multiplexer according to the invention, and 10 - Figures 4 to 5 relate to a diagram. pin affection of an analog multiplexer according to the invention and a mode of operation called "cold spare". FIG. 1 shows a diagram of the different stages of an analog multiplexer MA, for example 16 channels, according to the invention incorporated in an integrated circuit CI. The multiplexer comprises a switching stage 3. The switching stage 3 contains several switching circuits CCi associated with the corresponding channels, for example 16 switching circuits CC1 to CC16, and connected between several inputs BE1 to BE16 and an output BS. As a function of a selection signal SS applied to the corresponding channel, the corresponding switching circuit is on to transmit the input signal of the corresponding channel to the output of the analog multiplexer, or is blocked.
    [0009] A level 1 address and conversion input stage receives the digital address AO to A3 of a channel to be processed, an activation signal ENb and a reference signal VREF at its inputs. The activation signal is then converted to the selection signal SS. A decoding stage 2 then transmits the selection signal SS SS to the corresponding analog switching circuit of the channel to be processed as a function of the digital address received from the preceding stage. Advantageously, the switching stage 3 also comprises a voltage selection circuit CST configured to ensure the proper operation of the analog multiplexer, especially in the so-called "cold spare" mode 3030155. The architecture and operation of the CST voltage selection circuit will be detailed below. The analog multiplexer furthermore has a protection stage 4 protecting the whole of the analog multiplexer against possible electrostatic discharges. Since all the switching circuits CC1 to CC16 located in the switching stage 3 are identical, one of the switching circuits CCi will now be described with particular reference to FIGS. 2 to 3.
    [0010] As illustrated in FIG. 2, the switching circuit CCi comprises: a first NMOS type switching module 5 having an on state and a blocked state; a second PMOS type switching module 6 having an on state and a blocked state, - a first control module 7 dedicated to the first switching module of the NMOS type 5 and - a second control module 8 dedicated to the second switching module of the PMOS type 6.
    [0011] The selection signal SS here in fact comprises a first binary control signal SCB1 and a second binary control signal SCB2. The two signals are complementary as will be seen in more detail below. When the multiplexer is in a normal operating mode, i.e. powered by the non-zero supply voltage Vdd and the first bit control signal SCB1 is low and therefore the second binary signal SCB2 is in the high state, the switching circuit CCi is in its on state. On the other hand, when the first binary control signal SCB1 is high and therefore the second binary control signal SCB2 is low, the switching circuit CCi is in its off state. The two switching modules 5 and 6 are connected in parallel between the corresponding input BEi and the output BS. This structure having on one side an NMOS switch and on the other a PMOS switching advantageously makes it possible to ensure the operation of the switching circuit CCi throughout the dynamic range of the input signals.
    [0012] The first switching module 5 comprises two NMOS transistors 51 and 52 with extended drain, of conventional structure and known per se, connected in series between the input BEi and the output BS. The sources and substrates of the two NMOS transistors 51 and 52 are mutually connected.
    [0013] By analogy, the second switching module 6 comprises two extended drain PMOS transistors 61 and 62 connected in series between the input BE 1 and the output BS and having their sources and substrates mutually connected. Thus, the switching modules can support high voltage input and output signals, for example up to 16 V. The use of the extended drain transistors 51, 52, 61 and 62 makes it possible to support such signals. high voltage input (for example up to 16 volts) while using a low voltage technology to supply the grids these transistors (typically of the order of a few volts). The input and output impedances are also high because the corresponding input and the output of the switching module are connected to the drains of the extended-drain transistors.
    [0014] Furthermore, since the sources and substrates of these extended drain transistors 51, 52, 61 and 62 of each switching module are mutually connected to an internal node 50 and 60 (a device commonly referred to by those skilled in the art as "back to back switch"), the gate-source and source-substrate voltages of the extended-drain transistors can be controlled, which makes it possible to obtain high linearity for the switching modules and to reduce as much as leak currents when the switching modules are in their off state, as will be seen in more detail below.
    [0015] The first control module 7 shown in FIG. 2 comprises a first control block 9, controllable by the first binary control signal SCB1, and comprising two extended drain NMOS auxiliary transistors 91 and 92. The drain of the NMOS auxiliary transistor 91 is connected to the gates of the two NMOS transistors 51 and 52 with extended drain of the first switching module 5. The drain of the NMOS auxiliary transistor 92 is connected to the sources and substrates of the two NMOS transistors 51 and 52 with extended drain of the first switching module 5. The gates of the auxiliary NMOS transistors 91 and 92 are controllable by the first binary control signal SCB1 and the sources of these auxiliary transistors are connected to the ground Vss. When the first bit control signal SCB1 has a first logic value, for example 3.3 V (high state), the auxiliary NMOS transistors 91 and 92 are in their on state and the gates and substrates of the NMOS transistors 51 and 52 of the first switching module 5 are drawn to the ground Vss. As a result, the NMOS transistors 51 and 52 of the first switching module 5 are blocked and the first switching module 5 is then placed in the off state. The leakage currents are advantageously limited because the grids, sources and substrates of NMOS 51 and 52 are grounded. The first control module 7 further comprises a first input block 10 comprising a follower-mounted extended-drain PMOS transistor 101 whose gate is connected to said corresponding input BEi. Its drain is connected to the ground Vss and its source is connected to the gates of the NMOS transistors 51 and 52 through a first high voltage diode D1 and the first supply voltage Vdd through a current source.
    [0016] A second high voltage diode D2 is connected between the source and the gate of the PMOS transistor 101. The two diodes D1 and D2 are intended to provide protection for the transistor 101 and also additional protection for the transistors 51 and 52.
    [0017] When the first binary control signal SCB1 has its second logic value, for example OV (low state), the transistors 91 and 92 are off. The voltage Vgnmos of the gates of the NMOS transistors 51 and 52 is equal to the difference between the voltage of the input signal and the threshold voltage of the PMOS transistor 101. The first switching module of the NMOS type 5 is therefore capable of being passing. Nevertheless, the voltage Vgnmos is also limited by the supply voltage Vdd. If the voltage of the input signal is close to the voltage Vdd, the voltage Vgnmos will not be large enough that the NMOS transistors 51 and 52 are effectively in the on state. In this case, the first switching module 5 is in its off state and can not transmit the input signal to the output. The signal will then be transmitted by the second switching module 6. The architecture of the second control module 8, controllable by the second binary control signal SCB2, which is complementary to the first binary control signal SCB1, is now described. The second control module 8 is powered by a second supply voltage Vmax which is supplied by the voltage selection circuit CST and which, as will be seen below, is equal to the greater of the voltage Vdd and voltages present at terminals BEi and BS (Vmax = Max (VBEi, VBS, Vdd)). When the multiplexer is in a normal operating mode, i.e. powered by the non-zero supply voltage Vdd, the voltage Vmax is equal to Vdd. The second control module 8 comprises a comparator 80 whose two inputs are respectively coupled to the first and second binary control signals SCB1 and SCB2. The positive power supply terminal 30 is connected to said second supply voltage Vmax. The negative power supply terminal is connected to the ground Vss. A first output of the comparator 80 is connected to the gate of an extended drain PMOS control transistor 81 whose source is connected to the second supply voltage Vmax and whose drain is connected to the sources and substrates of the two transistors. PMOS 61 and 62 with extended drain of the second switching module 6. A second output of the comparator 80 is coupled to the gates 5 of the two PMOS transistors 61 and 62 of the second switching module 6. When the second control signal SCB2 has a first value logic, for example 0 V, the Vgpmos voltage of the gates of the two PMOS transistors 61 and 62 is equal to the second supply voltage Vmax and the gate voltage of the control transistor 81 equal to a static voltage equal, for example, to 12 V. This static voltage is chosen so that, when the signal SCB2 has a high state, the transistors 61 and 62 are on for input signals close to the power supply voltage. Vdd and so that the gate-source voltages of the PMOS transistors 61 and 62 do not exceed a fixed limit, for example 4.8 V. Vmax here Vdd, for example 16 V, the control transistor 81 is therefore in state and the voltage of the sources and substrates of the two PMOS transistors 61 and 62 is pulled to the second supply voltage Vmax. Since the voltage Vgpmos of the gates of the two PMOS transistors 61 and 62 is also equal to the second supply voltage Vmax, the second PMOS type switching module 6 is in the off state and the leakage currents are minimized because the 25 gate voltages, source and substrate of PMOS transistors 61 and 62 are drawn at Vdd. When the second binary control signal SCB2 switches to its second logic value (high state), for example 3.3 V, the voltage Vgpmos is equal to 12 V and the gate voltage of the control transistor 81 is equal to the second voltage d Vmax supply (Vdd). In this circumstance, the control transistor 81 is in the off state. As a result, the sources and substrates of the PMOS transistors 61 and 62 of the second switching module 6 are floated 3030155 11 and the second switching module of the PMOS type 6 is likely to be in the on state. In fact, the second PMOS type switching module 6 is only really active when the voltages of the input signals 5 exceed the sum of the static voltage (12V) and the threshold voltage of the PMOS transistors 61 and 62. second switching module 6. The second switching module 6 is thus configured to take over from the first switching module 5 when the voltages of the input signals are close to the first supply voltage Vdd, typically for signals included between about 13 volts and Vdd (16 volts). Thus, depending on the voltage of the input signal, when the signals SCB1 and SCB2 respectively have their logic states low and high, either one of the two switching modules 5 and 6 is on or off and the other blocked or passing, either the two switching modules are on. In most cases, the first supply voltage Vdd is larger than those of the input and output signals.
    [0018] However, when the analog multiplexer is in "cold spare" mode and completely off, the first supply voltage Vdd is equal to zero. The voltages of the input and output signals can then be larger than that of Vdd. To ensure the operation of the second PMOS type switching module 6, the switching stage 3 furthermore comprises at least one voltage selection circuit CST such as that illustrated in FIG. 3. The voltage selection circuit CST comprises here an additional PMOS TA extended drain transistor whose gate is connected to its source by a resistor and powered by a current source. The source of the additional transistor TA is connected to all the inputs BEi and to the output BS of the switching stage 3 by diodes D3 and D4 in reverse. The source of the additional transistor TA is intended to deliver the second supply voltage Vmax.
    [0019] As explained above, when the supply voltage Vdd is greater than the largest of the corresponding input and output signals, the additional transistor PMOS TA operates as a switch and there is There is no voltage drop between its drain and its source. The second supply voltage Vmax is then Vdd. In the "cold spare" mode, the supply voltage Vdd is equal to 0 and the current source is therefore in off mode. The second supply voltage Vmax is then equal to the largest voltage of the input voltage present at the corresponding input BEi and the output voltage minus the threshold voltage of the diode D3 or D4. Thus, the greatest voltage among the first supply voltage Vdd and the voltages of the input and output signals is always selected by this voltage selection circuit CST. Referring now to Figures 4 to 5 to illustrate a pin assignment scheme of the analog multiplexer according to the invention and an embodiment of the two analog multiplexers so-called "cold spare" mode.
    [0020] FIG. 4 effectively illustrates an analog multiplexer pin assignment scheme just described having 16 inputs IN1-IN16 (corresponding to the 16 BEI-BE16 terminals of FIG. 1) and one output. The ADDR pins AO to A3 are configured to receive the digital address of the channel to be processed and the ENb pin 25 to activate the multiplexer. There are also the pins related to supply voltage signals such as + Vs, -Vs, VREF and GND. The "cold spare" mode of the analog multiplexer B is illustrated in FIG. 5. In this figure, an analog multiplexer A is in operation and powered by the first supply voltage (Vdd = 16 V) and the analog multiplexer B is completely off (Vdd = 0 V, VENb = 0 V). In this circumstance, the two binary control signals SCB1 and SCB2 are also 0 V. As a result, the second PMOS type switching module 6 of the multiplexer B is in its off state. As for the first switching module of the NMOS type 5, since the supply voltage Vdd is equal to 0V, it is also in its off state.
    [0021] Moreover, the leakage currents are well reduced by controlling the gate-source and substrate-source voltages of the transistors 51, 52, 61 and 62 of the two switching modules 5 and 6, and, with regard to the module of FIG. switching PMOS 6 through the voltage selection circuit CST which imposes Vmax = Max (VBEi, VBS, Vdd = 10 0). Therefore, if the multiplexer A delivers a signal to the multiplexer B being completely extinguished, the internal components of the multiplexer B will not be destroyed. On the other hand, since V max = Max (VBE 1, VBS, Vdd = 0), and the sources and substrates of PMOS transistors 61 and 62 of multiplexer B are drawn at V max and that transistors 51 and 52 are off, even if a voltage is present on one of the inputs BEi or on the output BS of the multiplexer B due to a connection with a pin of the multiplexer A, any current consumption at the input 20 and the output of the multiplexer B is zero near leaks, that is to say below a defined threshold for example of the order of 0.1% of a normal current consumption in the presence of Vdd (16V). The analog multiplexer B in so-called "cold spare" mode will not therefore disturb the normal operation of the analog multiplexer A. It should be noted that the outputs of the analog multiplexers are bidirectional. One of the inputs or the output of the multiplexer A could be coupled with the output of the multiplexer B and vice versa.
    [0022] It is thus possible according to one aspect of the invention to obtain a high voltage analog multiplexer which can be realized with a low voltage control technology, compatible with the "cold spare" mode and having good linearity of the switch modules throughout the 3030155 14 dynamic range of signals, in particular by controlling the gate-source voltage of the transistors of these switching modules. The invention is not limited to the embodiments which have just been described but encompasses all the variants.
    [0023] Thus, while a single voltage selection circuit CST connected to all the inputs has been described, it would be possible to provide several identical voltage selection circuits respectively assigned to several groups of inputs.
    权利要求:
    Claims (11)
    [0001]
    REVENDICATIONS1. Analogue multiplexer, comprising several inputs (BE1 to BE16) and an output (BS) and a plurality of switching circuits respectively connected between the inputs (BE1 to BE16) and said output (BS), characterized in that each switching circuit comprises a first an NMOS-type switching module (5) having an on state and a off state and a second PMOS switching module (6) having an on state and a off state connected in parallel between the corresponding input (BEi) and the output (BS), a first control module (7) intended to be powered by a first supply voltage (Vdd) and configured to reduce the leakage currents of the first switching module (5) when the first switching module (5) is in its off state, a second control module (8) to be powered by a second supply voltage (Vmax) and configured to reduce leakage currents of the second m switching odule (6) when the second switching module (6) is in its off state, and the multiplexer further comprises at least one voltage selection circuit (CST) configured to output the second supply voltage (Vmax) equal to the greater of the first supply voltage (Vdd) and the voltages present at the input and at the output.
    [0002]
    An analog multiplexer according to claim 1, wherein the first control module and the second control module are further configured so that, when the first supply voltage (Vdd) is zero, the two switching modules are blocked and any current consumption at the input (BEi) and the output (BS) is zero.
    [0003]
    An analog multiplexer according to claim 1, wherein the first control module and the second control module are further configured so that, when the first supply voltage (Vdd) is zero, the two switching modules are blocked and any current consumption at the input (BEi) and the output (BS) is less than. a threshold 3030155 - 16 of the order of 0.1% of a normal consumption of current in the presence of a first non-zero supply voltage (Vdd).
    [0004]
    An analog multiplexer according to one of the preceding claims, wherein said first switching module (5) comprises two extended drain NMOS transistors (51 and 52) connected in series between the input (BEi) and the output (BS). ) and having their sources and substrates mutually connected, and said second switching module (6) comprises two extended drain PMOS transistors (61 and 62) connected in series between the input (BEi) and the output (BS) and having 10 their sources and substrates mutually connected.
    [0005]
    An analog multiplexer according to claim 4, wherein said first control module (7) comprises a first control block (8) controllable by a first binary control signal (SCB1) and configured for when the first binary control signal (SCB1) has a first logic value, ground (Vss) the gates and substrates of the NMOS transistors (51 and 52) of the first switching module (5) so as to place it in its off state.
    [0006]
    The multiplexer according to claim 4 or 5, wherein the first control module (7) further comprises a first input block (8) connected to said corresponding input (BEi) and configured for when the first control signal binary (SCB1) has its second logic value corresponding to an on state of the first switching module (5), slaving the voltages (Vgnmos) of gates 25 of the NMOS transistors (51 and 52) of the first switching module (5) on the voltage present at the input (BEi) and limit these gate voltages (Vgnmos) to the first supply voltage (Vdd).
    [0007]
    The analog multiplexer according to one of the preceding claims, wherein said second control module (8) is controllable by a second binary control signal (SCB2) and configured for when the second binary control signal (SCB2) has a first logic value, pull at the second power supply voltage (Vmax), the gates and the substrates of the PMOS transistors (61 and 62) of the second switching module (6) so as to place it in its off state.
    [0008]
    The multiplexer according to claim 7, wherein the second control module (8) is further configured for when the second binary control signal (SCB2) has its second logic corresponding to an on state of the second switching module ( 6), leave the sources and substrates of the PMOS transistors (61 and 62) of the second switching module (6) floating and apply to the gates of these PMOS transistors (61 and 62) of the second switching module (6) a voltage gate (Vgnmos) adjacent to the first supply voltage (Vdd).
    [0009]
    The analog multiplexer according to one of claims 5 or 6 taken in combination with one of claims 7 or 8, wherein the first binary control signal (SCB1) and the second binary control signal (SCB2) are complementary signals.
    [0010]
    An analog multiplexer according to claim 1, wherein said at least one voltage selection circuit (CST) comprises an extended drain PMOS (TA) additional transistor whose gate is connected to its source by a resistor and supplied by a resistor. current source, the source of the additional transistor (TA) being connected to said input (BEi) and to the output (BS) by diodes (D3 and D4) in reverse, the source being intended to deliver said second supply voltage (Vmax).
    [0011]
    Analog multiplexer according to one of the preceding claims, implemented in an integrated manner.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    EP1024596A1|1999-01-29|2000-08-02|Fairchild Semiconductor Corporation|Overvoltage/undervoltage tolerant transfer gate|
    US20020041198A1|2000-08-25|2002-04-11|Michael Parris|Area efficient redundancy multiplexer circuit technique for integrated circuit devices providing significantly reduced parasitic capacitance|
    US6538867B1|2000-11-15|2003-03-25|Fairchild Semiconductor Corporation|FET switch with overvoltage protection|
    US20050057283A1|2003-09-05|2005-03-17|Broadcom Corporation|Sample and hold circuit based on an ultra linear switch|
    US20080231341A1|2007-03-23|2008-09-25|Miske Myron J|Over-voltage tolerant pass-gate|US9979396B1|2017-02-23|2018-05-22|StmicroelectronicsSas|Bidirectional analog multiplexer|JP4582890B2|2000-09-28|2010-11-17|ルネサスエレクトロニクス株式会社|Analog switch circuit, analog multiplexer circuit, AD converter, and analog signal processing system|
    US7119601B2|2004-08-04|2006-10-10|Texas Instruments Incorporated|Backgate pull-up for PMOS pass-gates|
    JP4832965B2|2006-06-07|2011-12-07|パナソニック株式会社|Switch circuit device, radio circuit device using the switch circuit device, and sampling circuit device|JP2016127573A|2015-01-08|2016-07-11|株式会社東芝|Analog switch and multiplexer|
    DE102015122109A1|2015-12-17|2017-06-22|Tdk-Micronas Gmbh|Voltage-resistant switch|
    US10200041B2|2016-11-01|2019-02-05|Analog Devices Global|Analog multiplexer|
    US10624246B2|2017-08-03|2020-04-14|Bae Systems Information And Electronic Systems Integration Inc.|Apparatuses for implementing cold-sparable SerDes|
    US10924116B1|2019-10-09|2021-02-16|Semiconductor Components Industries, Llc|Analog switch multiplexer systems and related methods|
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    FR1462317A|FR3030155B1|2014-12-12|2014-12-12|ANALOG MULTIPLEXER|FR1462317A| FR3030155B1|2014-12-12|2014-12-12|ANALOG MULTIPLEXER|
    US14/837,279| US9520869B2|2014-12-12|2015-08-27|Analog multiplexer|
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